In the fabrication of semiconductor devices from a silicon wafer, a variety of semiconductor processing equipment and tools are utilized. One of these processing tools is used for polishing thin, flat semiconductor wafers to obtain a planarized surface. A planarized surface is highly desirable on a shadow trench isolation (STI) layer, inter-layer dielectric (ILD) or on an inter-metal dielectric (IMD) layer, which are frequently used in both memory and logic devices. The planarization process is important since it enables the subsequent use of a high-resolution lithographic process to fabricate the next-level circuit. The accuracy of a high resolution lithographic process can be achieved only when the process is carried out on a substantially flat surface. The planarization process is therefore an important processing step in the fabrication of semiconductor devices.
A global planarization process can be carried out by a technique known as chemical mechanical polishing, or CMP. The process has been widely used on STI, ILD or IMD layers in fabricating modern semiconductor devices. A CMP process is performed by using a rotating platen in combination with a polishing head. The process is used primarily for polishing the front surface or the device surface of a semiconductor wafer for achieving planarization and for preparation of the next level processing. A wafer is frequently planarized one or more times during a fabrication process in order for the top surface of the wafer to be as flat as possible. A wafer can be polished in a CMP apparatus by being placed on a carrier and pressed face down on a polishing pad covered with a slurry of fumed, colloidal silica, aluminum, or CeO2.
A polishing pad used on a rotating platen is typically constructed in two layers overlying a platen, with a resilient layer as an outer layer of the pad. The layers are typically made of a polymeric material such as polyurethane and may include a filler for controlling the dimensional stability of the layers. A polishing pad is typically made several times the diameter of a wafer in a conventional rotary CMP, while the wafer is kept off-center on the pad in order to prevent polishing of a non-planar surface onto the wafer. The wafer itself is also rotated during the polishing process to prevent polishing of a tapered profile onto the wafer surface. The axis of rotation of the wafer and the axis of rotation of the pad are deliberately not collinear; however, the two axes must be parallel. It is known that uniformity in wafer polishing by a CMP process is a function of pressure, velocity and concentration of the slurry used.
A CMP process is frequently used in the planarization of an STI, ILD or IMD layer on a semiconductor device. Such layers are typically formed of a dielectric material. A most popular dielectric material for such usage is silicon oxide. In a process for polishing a dielectric layer, the goal is to remove typography and yet maintain good uniformity across the entire wafer. The amount of the dielectric material removed is normally between about 2000 A and about 10,000 A. The uniformity requirement for STI, ILD or IMD polishing is very stringent since non-uniform dielectric films lead to poor lithography and resulting window-etching or plug-formation difficulties. The CMP process has also been applied to polishing metals, for instance, in tungsten plug formation and in embedded structures. A metal polishing process involves a polishing chemistry that is significantly different than that required for oxide polishing.
Important components used in CMP processes include an automated rotating polishing platen and a wafer holder, which both exert a pressure on the wafer and rotate the wafer independently of the platen. The polishing or removal of surface layers is accomplished by a polishing slurry consisting mainly of fumed, colloidal silica or CeO2 suspended in deionixed water or alkali solution. The slurry is frequently fed by an automatic slurry feeding system in order to ensure uniform wetting of the polishing pad and proper delivery and recovery of the slurry. For a high-volume wafer fabrication process, automated wafer loading/unloading and a cassette handler are also included in a CMP apparatus.
As the name implies, a CMP process executes a microscopic action of polishing by both chemical and mechanical means. While the exact mechanism for material removal of an oxide layer is not known, it is hypothesized that the surface layer of silicon oxide is removed by a series of chemical reactions which involve the formation of hydrogen bonds with the oxide surface of both the wafer and the slurry particles in a hydrogenation reaction; the formation of hydrogen bonds between the wafer and the slurry; the formation of molecular bonds between the wafer and the slurry; and finally, the breaking of the oxide bond with the wafer or the slurry surface when the slurry particle moves away from the wafer surface. It is generally recognized that the CMP polishing process is not a mechanical abrasion process of slurry against a wafer surface.
While the CMP process provides a number of advantages over the traditional mechanical abrasion type polishing process, a serious drawback for the CMP process is the difficulty in controlling polishing rates at different locations on a wafer surface. Since the polishing rate applied to a wafer surface is generally proportional to the relative rotational velocity of the polishing pad, the polishing rate at a specific point on the wafer surface depends on the distance from the axis of rotation. In other words, the polishing rate obtained at the edge portion of the wafer that is closest to the rotational axis of the polishing pad is less than the polishing rate obtained at the opposite edge of the wafer. Even though this is compensated for by rotating the wafer surface during the polishing process such that a uniform average polishing rate can be obtained, the wafer surface, in general, is exposed to a variable polishing rate during the CMP process.
Recently, a chemical mechanical polishing method has been developed in which the polishing pad is not moved in a rotational manner but instead, in a linear manner. It is therefore named as a linear chemical mechanical polishing process, in which a polishing pad is moved in a linear manner in relation to a rotating wafer surface. The linear polishing method affords a more uniform polishing rate across a wafer surface throughout a planarization process for the removal of a film layer from the surface of a wafer. One added advantage of the linear CMP system is the simpler construction of the apparatus, and this not only reduces the cost of the apparatus but also reduces the floor space required in a clean room environment.
A typical conventional CMP apparatus 90 is shown in FIG. 1 and includes a base 100; polishing pads 210a, 210b, and 210c provided on the base 100; a head clean load/unload (HCLU) station 360 which includes a load cup 300 for the loading and unloading of wafers (not shown) onto and from, respectively, the polishing pads; and a head rotation unit 400 having multiple polishing pads 410a, 410b, 410c and 410d for holding and fixedly rotating the wafers on the polishing pads.
The three polishing pads 210a, 210b and 210c facilitate simultaneous processing of multiple wafers in a short time. Each of the polishing pads is mounted on a rotatable carousel (not shown). Pad conditioners 211a, 211b and 211c are typically provided on the base 100 and can be swept over the respective polishing pads for conditioning of the polishing pads. Slurry supply arms 212a, 212b and 212c are further provided on the base 100 for supplying slurry to the surfaces of the respective polishing pads.
The polishing heads 410a, 410b, 410c and 410d of the head rotation unit 400 are mounted on respective rotation shafts 420a, 420b, 420c, and 420d which are rotated by a driving mechanism (not shown) inside the frame 401 of the head rotation unit 400. The polishing heads hold respective wafers (not shown) and press the wafers against the top surfaces of the respective polishing pads 210a, 210b and 210c. In this manner, material layers are removed from the respective wafers. The head rotation unit 400 is supported on the base 100 by a rotary bearing 402 during the CMP process.
The load cup 300 is detailed in FIG. 1 and includes a pedestal support column 312 that supports a circular pedestal 310 on which the wafers are placed for loading of the wafers onto the polishing pads 210a, 210b and 210c, and unloading of the wafers from the polishing pads. A pedestal film 313 is typically provided on the upper surface of the pedestal 310 for contacting the patterned surface (the surface on which IC devices are fabricated) of each wafer. Fluid openings 314 extend through the pedestal 310 and pedestal film 313. The bottom surfaces of the polishing heads 410a, 410b, 410c and 410d and the top surface of the pedestal film 313 are washed at the load cup 300 by the ejection of washing fluid through the fluid openings 314.
In typical operation, the CMP apparatus 90 is used to remove material from a layer (not shown) on each wafer in order to reduce the thickness of the layer to a desired target thickness. Accordingly, the pre-CMP thickness of the layer is initially measured, and the estimated polish time and polish recipe, along with the target thickness for the layer on each wafer, are programmed into a CLC (closed-loop controller) 1, shown in FIG. 2. Each wafer is mounted on a polishing head 410a, 410b, 410c or 410d and sequentially polished against the polishing pads 210a, 210b and 210c, respectively, of the CMP apparatus 90. The polishing pads progressively remove material from and reduce the thickness of the layer on the wafer. The polishing process is shown in FIG. 2, wherein S1 indicates the first polishing step on the polishing pad 210a; S2 indicates the second polishing step on the polishing pad 210b; and S3 indicates the third polishing step on the polishing pad 210c. The CLC 1 controls the polish time and other aspects of the polishing recipe at each polishing step in the sequence. After the polishing sequence is completed the wafer may be subjected to post-CMP cleaning, as indicated in step S4.
After post-CMP cleaning, the wafer may be subjected to in-line metrology, as indicated in step S5, to measure the post-CMP thickness of the polished layer. The post-CMP thicknesses of the layers among the wafers in a given wafer lot have a tendency to vary somewhat from each other, due to the inherent differences in the material removal rate from one polishing sequence to another. Accordingly, the measured post-CMP thickness of the layer on each wafer is transmitted as a feedback signal 2 to the CLC 1, which uses the pre-CMP thickness, post-CMP thickness and polish time for each wafer to calculate the material removal rate for the layer on the wafer. The CLC 1 then uses the calculated material removal rate for the wafer to adjust the polishing time for the next wafer to be polished at the polishing steps S1–S3. Accordingly, a feedback adjustment to the polish time is made to the process recipe for each successive wafer in a wafer lot, and is based on the material removal rate calculated for the layer on the previous wafer. This continuous feedback for each wafer in the lot contributes to uniformity in the quantity of material removed from the layers among the multiple wafers in the lot.
The continuous feedback mechanism described above is based on a single-variable (material removal rate) algorithm and is suitable for CMP applications in which material is removed from a single layer on a wafer. However, the continuous feedback mechanism is unsuitable for more complex processes, such as STI (shallow trench isolation) CMP processes. In an STI CMP process, three variables must be taken into account when calculating the proper material removal rate: the trench depth, the HDP oxide thickness and the SiN thickness. Use of the single-variable continuous feedback mechanism in an STI CMP process frequently causes over-prediction and over-adjustment to the material removal rate for succeeding wafers in a lot. Accordingly, an improved method for controlling a CMP process is needed.
An object of the present invention is to provide an improved CMP process control method.
Another object of the present invention is to provide an improved, one-time feedback CMP process control method which contributes to uniformity in the quantity of material removed from wafers in a lot during semiconductor processing.
Still another object of the present invention is to provide a one-time feedback CMP process control method which is suitable for complex processes such as STI (shallow trench isolation) fabrication procedures.
Yet another object of the present invention is to provide an improved one-time feedback CMP process control method which eliminates or substantially reduces run-to-run process variations in a CMP process.
A still further object of the present invention is to provide an improved, one-time feedback CMP process control method which includes a one-time polishing time feedback adjustment for all wafers in a lot to facilitate greater between-wafer uniformity in the quantity of material removed from the wafers in a CMP process.
Yet another object of the present invention is to provide an improved CMP process control method which is characterized by precise adjustment in the process time and material removal rate in the chemical mechanical polishing of wafers.
A still further object of the present invention is to provide an improved CMP process control method which may include the polishing of pilot wafers in a lot to determine the divergence of the thickness of each wafer from a target thickness and the material removal rate of each polishing head in the apparatus; calculating a compensation time using the average divergence and the average material removal rate; calculating an update time by adding the compensation time to the original process time; and polishing the remaining wafers in the lot according to the update time.
Yet another object of the present invention is to provide an improved CMP process control method which in one embodiment includes determining a compensation time for each of multiple polishing heads or wafer carriers in a CMP apparatus using pilot wafers in a lot; calculating an update process time for each polishing head by adding the original process time to the compensation time for the polishing head; and processing remaining wafers in the lot using the update process time.